CSRW - RISC-V instruction reference

csrwWrite control and status register Pseudo-instruction
Writes t1 into the CSR and discards the value it held before.
RISC-V manual: csrrw 
Used in When an instruction cannot be carried outRISC-V assembly
 
Forms  csrw ,   
Operands t1 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
csr A control and status register, written by name or number, such as fcsr, fflags, frm, cycle, time, instret, ustatus, uepc, ucause or utval. See the supported registers. 
 # Initialize fcsr to 0, apply csrw with mask 1, then read fcsr into t2 (1).
.text
li t3, 0
csrw t3, fcsr
li t1, 1
csrw t1, fcsr
csrr t2, fcsr