ADDW - RISC-V instruction reference

addwAdd word (32-bit) RV64 only
Adds the low 32 bits of t2 and t3 and sign-extends the 32-bit sum into t1 (RV64 only).
RISC-V manual: addw 
Used in Going 64-bitRISC-V assembly
 
Forms  addw , ,   
Operands t1 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
t2 An integer register. It may be the same register as t1. 
t3 An integer register. It may be the same register as t1. 
This example runs on RV64.
 .text
li t0, 2147483647
li t1, 1
# t0=2147483647, t1=1; addw writes -2147483648 (0xFFFFFFFF80000000) to t2.
addw t2, t0, t1