CSRRCI - RISC-V instruction reference

csrrciAtomic read/clear CSR immediate 
Reads the CSR into t0 and clears the CSR bits that are set in a 5-bit constant, as one atomic step.
RISC-V manual: csrrci 
Forms  csrrci , ,   
Operands t0 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
csr A control and status register, written by name or number, such as fcsr, fflags, frm, cycle, time, instret, ustatus, uepc, ucause or utval. See the supported registers. 
imm5 An unsigned 5-bit immediate, 0 to 31, used for values such as a shift count or a CSR immediate. 
 # Initialize fcsr=1; csrrci returns old fcsr in t0 and leaves fcsr=0.
.text
li t3, 1
csrw t3, fcsr
csrrci t0, fcsr, 1