CSRS - RISC-V instruction reference

csrsSet bits in control and status register Pseudo-instruction
Sets the CSR bits that are set in t1, leaving the other bits unchanged.
RISC-V manual: csrrs 
Forms  csrs ,   
Operands t1 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
csr A control and status register, written by name or number, such as fcsr, fflags, frm, cycle, time, instret, ustatus, uepc, ucause or utval. See the supported registers. 
 # Initialize fcsr to 0, apply csrs with mask 1, then read fcsr into t2 (1).
.text
li t3, 0
csrw t3, fcsr
li t1, 1
csrs t1, fcsr
csrr t2, fcsr