CSRRC - RISC-V instruction reference

csrrcAtomic read/clear CSR 
Reads the CSR into t0 and clears the CSR bits that are set in t1, as one atomic step.
RISC-V manual: csrrc 
Forms  csrrc , ,   
Operands t0 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
csr A control and status register, written by name or number, such as fcsr, fflags, frm, cycle, time, instret, ustatus, uepc, ucause or utval. See the supported registers. 
t1 An integer register. It may be the same register as t0. 
 # Initialize fcsr=1; csrrc returns old fcsr in t0 and leaves fcsr=0.
.text
li t3, 1
csrw t3, fcsr
li t1, 1
csrrc t0, fcsr, t1