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srl

Shift right logical

Shifts a register or memory byte right one bit, copying bit 0 to C and putting zero into bit 7.

Used in
SZHP/VNC ●●0●0●
  • ● set from the result
  • 0 always 0

Forms

  • The contents of r are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7.

  • srl 2 bytes · 15 cycles

    The contents of (HL) are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7.

  • The contents of the memory location pointed to by IX plus dd are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7.

Undocumented 1 row

Left out of Zilog's manual, but the Z80 runs them, and so does this emulator.

  • The contents of the memory location pointed to by IX plus dd are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7. The result is then stored in r.

Operands

r
An 8-bit register: a, b, c, d, e, h or l.
(hl)
The byte in memory at the address stored in hl. More
(ix+dd)
The byte in memory at ix + dd, where dd is a signed displacement from -128 to 127, for example (ix+5) or (ix-3). (iy+dd) works the same way. More
        .org 0x8000
        ld b, 3
        srl b
        halt