LD - Z80 instruction reference

SZHP/VNC ––––––

Changes no flag

The rows that do otherwise show their own flags.

Forms

ld , 1 byte · 4 cycles

The contents of r' are loaded into r.
ld , 2 bytes · 7 cycles

Loads nn into r.
ld , 1 byte · 7 cycles

The contents of (HL) are loaded into r.
ld , 3 bytes · 19 cycles

Loads the value pointed to by IX plus dd into r.
ld , 1 byte · 7 cycles

The contents of r are loaded into (HL).
ld , 3 bytes · 19 cycles

Stores r to the memory location pointed to by IX plus dd.
ld , 2 bytes · 10 cycles

Loads nn into (HL).
ld , 4 bytes · 19 cycles

Stores nn to the memory location pointed to by IX plus dd.
ld a, (bc) 1 byte · 7 cycles

Loads the value pointed to by BC into A.
ld a, (de) 1 byte · 7 cycles

Loads the value pointed to by DE into A.
ld a, () 3 bytes · 13 cycles

Loads the value pointed to by nnnn into A.
ld (bc), a 1 byte · 7 cycles

Stores A into the memory location pointed to by BC.
ld (de), a 1 byte · 7 cycles

Stores A into the memory location pointed to by DE.
ld (), a 3 bytes · 13 cycles

Stores A into the memory location pointed to by nnnn.
ld a, i 2 bytes · 9 cycles S●Z●H0P/V●N0

Stores the value of register I into A.
ld a, r 2 bytes · 9 cycles S●Z●H0P/V●N0

Stores the value of register R into A.
ld i, a 2 bytes · 9 cycles

Stores the value of A into register I.
ld r, a 2 bytes · 9 cycles

Stores the value of A into register R.
ld , 3 bytes · 10 cycles

Loads nnnn into rr.
ld , 4 bytes · 14 cycles

Loads nnnn into register IX.
ld hl, () 3 bytes · 16 cycles

Loads the value pointed to by nnnn into HL.
ld , () 4 bytes · 20 cycles rr: bc de sp

Loads the value pointed to by nnnn into rr.
ld , () 4 bytes · 20 cycles

Loads the value pointed to by nnnn into IX.
ld (), hl 3 bytes · 16 cycles

Stores HL into the memory location pointed to by nnnn.
ld (), 4 bytes · 20 cycles rr: bc de sp

Stores rr into the memory location pointed to by nnnn.
ld (), 4 bytes · 20 cycles

Stores IX into the memory location pointed to by nnnn.
ld sp, hl 1 byte · 6 cycles

Loads the value of HL into SP.
ld sp, 2 bytes · 10 cycles

Loads the value of IX into SP.

Pseudo-instructions

Other spellings the assembler accepts; each form shows the instruction it becomes.

ld , 2 bytes · 8 cycles rr: bc de hl rr': bc de hl

The contents of rr' are loaded into rr.
ld bc, (hl) 4 bytes · 26 cycles

The contents of (HL) are loaded into BC.
ld (hl), 4 bytes · 26 cycles rr: bc de

The contents of rr are loaded into (HL).

Undocumented 4 rows

Left out of Zilog's manual, but the Z80 runs them, and so does this emulator.

ld , 3 bytes · 11 cycles

Loads nn into ixh/l.
ld , 2 bytes · 8 cycles r: a b c d e

The contents of ixh/l are loaded into r.
ld , 2 bytes · 8 cycles r: a b c d e

The contents of r are loaded into ixh/l.
ld , 2 bytes · 8 cycles

The contents of ixh/l' are loaded into ixh/l.

Operands

r: An 8-bit register: a, b, c, d, e, h or l. The placeholder r stands for an 8-bit register. In ld a, r and ld r, a, the literal r names the refresh register.
r': An 8-bit register: a, b, c, d, e, h or l. It may be the same register as r.
nn: An 8-bit immediate value, 0 to 255 or -128 to 127, written as a number, character constant or symbol. More
(hl): The byte in memory at the address stored in hl. More
(ix+dd): The byte in memory at ix + dd, where dd is a signed displacement from -128 to 127, for example (ix+5) or (ix-3). (iy+dd) works the same way. More
nnnn: A 16-bit value or address, 0 to 65535, written as a number or label. (nnnn) accesses memory at that address. More
rr: A register pair: bc, de, hl or sp.
ix: The ix index register. You can also use iy, with the same instruction size and timing. More
rr': A register pair: bc, de or hl. It may be the same pair as rr.
ixh/l: The high or low byte of ix: ixh or ixl. For iy, use iyh or iyl. More
ixh/l': Choose ixh or ixl again; the same half may be used twice. If the other operand uses iyh or iyl, choose from iyh or iyl here too.

        .org 0x8000
        ld bc, 0x9000
        halt1
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