Star on github
AI Chat

sc

Store conditional

Stores $t1 at the address $t2 plus an offset and sets $t1 to 1 if the store succeeds, or 0 if it fails.

Forms

  • sc , ()

Pseudo-instructions

The assembler turns these into one or more real instructions.

Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors.

Operands

$t1
Any general-purpose register, $0 to $31, using its numeric or named spelling, such as $8 or $t0 ($zero is $0; $ra is $31).
imm16
A signed 16-bit immediate, -32768 to 32767.
$t2
A general-purpose register. It may be the same register as $t1.
imm
An immediate value: a signed 16-bit value (-32768 to 32767), an unsigned 16-bit value (0 to 65535) or a 32-bit value (-2147483648 to 4294967295). The assembler chooses a supported encoding for the value and other operands; a pseudoinstruction may expand into several instructions.
label
A named address in the program, such as the start of a loop or a variable in .data.
imm32
A 32-bit immediate, -2147483648 to 4294967295. Pseudoinstruction expansion may overwrite $at, losing its previous value.

In real multi-processor hardware this can fail (setting $t1 = 0) if another processor modified the target location since the preceding 'll'. Always succeeds in this simulator.

.data
.align 2
value: .word 0
.text
# Reserve value with ll, then store 0x12345678 conditionally. Inspect $t0: 1 means success; memory contains 0x12345678.
la $t1, value
ll $t3, 0($t1)
li $t0, 0x12345678
sc $t0, 0($t1)